By Ricardo Lourenço, Nuno Lourenço, Nuno Horta
This paintings addresses the examine and improvement of an cutting edge optimization kernel utilized to analog built-in circuit (IC) layout. rather, this works describes the changes contained in the AIDA Framework, an digital layout automation framework totally constructed via on the built-in Circuits Group-LX of the Instituto de Telecomunicações, Lisbon. It focusses on AIDA-CMK, by way of improving AIDA-C, that is the circuit optimizer portion of AIDA, with a brand new multi-objective multi-constraint optimization module that constructs a base for a number of set of rules implementations. The proposed resolution implements 3 ways to multi-objective multi-constraint optimization, specifically, an evolutionary process with NSGAII, a swarm intelligence technique with MOPSO and stochastic hill mountain climbing process with MOSA. in addition, the applied constitution permits the simple hybridization among kernels reworking the former easy NSGAII optimization module right into a extra developed and flexible module helping a number of unmarried and multi-kernel algorithms. the 3 multi-objective optimization techniques have been confirmed with CEC2009 benchmarks to limited multi-objective optimization and confirmed with genuine analog IC layout difficulties. The completed effects have been in comparison by way of functionality, utilizing statistical effects acquired from a number of autonomous runs. eventually, a few hybrid techniques have been additionally experimented, giving a foretaste to a variety of possibilities to discover in destiny work.
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Extra resources for AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing
Also, it can be observed that the best between shuffle and sort by objective is dependent on the problem, where in CF1, CF2, and CF3 the shuffle method is better and in CF5, CF6, and CF7 the sort by objective tends to be better. To evaluate the performance of the multi-kernel algorithms four combinations of two kernels were tested. 2. In Fig. 6 the results obtained for the four multi-kernel combinations are presented. 46 5 Kernel Validation Using CEC2009 Benchmarks Fig. 3 Pareto fronts for problems with 30 variables: CF1–CF7 Fig.
1 Differential Ampliﬁer Circuit Problem Before moving to the circuit optimizations, a brief preliminary note on the ampliﬁer circuits considered is given. A common tradeoff in the design of ampliﬁers is between current (power) consumption and bandwidth (speed). 1), where GBW is the gain-bandwidth product, Cload is the load capacity, and IDD is the current consumption. By maximizing the FOM, the power consumption is minimized and the bandwidth product is maximized. This FOM is commonly used by designers to access the energy efﬁciency of the achieved solution.
Com (2014). Accessed 2014 4. : Eldo classic—foundry certiﬁed SPICE accurate circuit simulation. http://www. com/products/ic_nanometer_design/analog-mixed-signal-veriﬁcation/eldo/ (2014). Accessed 2014 5. : LAYGEN II: Analog ICs Layout Generator. Springer, Berlin (2013) 6. : IC veriﬁcation and signoff using calibre. com/products/ic_ nanometer_design/veriﬁcation-signoff/ (2014). Accessed 2014 7. : A fast and elitist multiobjective genetic algorithm: NSGA-II. Evol. Comput. IEEE Trans. 6(2), 182–197 (2002) 8.