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Additional info for 8-bit AVR Microcontroller with 1К Byte Flash ATtiny15L
If DDB5 is set (one), the pin is a open-drain output. • SCK/INT0/T0 – PORT B, Bit 2 In Serial Programming mode, this pin serves as the serial clock input, SCK. In Normal mode, this pin can serve as the external interrupt0 input. See the interrupt description for details on how to enable this interrupt. Note that activity on this pin will trigger the interrupt even if the pin is configured as an output. 52 ATtiny15L 1187F–AVR–06/05 ATtiny15L In Normal mode, this pin can serve as the external counter clock input.
30 ATtiny15L 1187F–AVR–06/05 ATtiny15L Timer/Counter1 Output Compare RegisterA – OCR1A Bit 7 6 5 4 3 2 1 0 $2E MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCR1A The Output Compare Register 1A is an 8-bit read/write register. The Timer/Counter Output Compare Register 1A contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match occurs only if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match.
To secure EEPROM integrity, the user is advised to use an external undervoltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a two-state write procedure must be followed. Refer to the description of the EEPROM Control Register for details of this. When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed. The EEPROM Address Register – EEAR Bit 7 6 5 4 3 2 1 0 $1E – – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial vAlue 0 0 X X X X X X EEAR • Bit 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero.